The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Integrated circuits (“ICs”) of a synchronized digital system (SDS) may include clocking systems that distribute clock signals to various circuits on or off the ICs. Clocked circuits respond to the assertion (or deassertion) of a clock signal. An IC may use clock gaters to inhibit operation of one or more clocked circuits for a predetermined number of clock cycles while the remainder of the IC continues to function.
Clock gaters can function as simple on/off switches that control whether or not a clock signal is received in the clocked circuit, thereby controlling whether or not the circuit operates. Clock gaters may buffer clock signals in response to assertion (or deassertion) of an enable signal and pass the clock signal in response to deassertion (or assertion) of the enable signal.
Referring now to FIG. 1, a clock source 10 of an IC system 12 provides clock signals to system devices, such as power-consuming circuits 14-1, 14-2, . . . , and 14-N (collectively referred to as power-consuming circuits 14). Exemplary power consuming circuits include dynamic logic circuits used to read and write data to memory. The clock source 10 also provides clock signals to power-consuming circuits 16-1, 16-2, . . . , and 16-M (collectively referred to as power-consuming circuits 16). Power-consuming circuits 14 may receive the clock signals via buffers 18, 20, whereas power-consuming circuits 16 may receive the clock signals via a buffer 22 and a clock gater 24.
The clock gater 24 may be selectively controlled (for example, enabled, disabled and/or run at low power) by enable signals (E) and test enable signals (TE) from a power management module 25. For example, the power management module 25 may determine that one or more of the power-consuming circuits 16 does not require a clock signal. The power management module 25 may enable the clock gater 24, which then may provide a constant low signal to the power-consuming circuits 16 instead of the clock signal.
The clock gater 24 may include one or more logic circuits. The logic circuits, which are also referred to as logic gates, may include inverters, AND gates, NAND gates, OR gates, NOR gates, etc. The logic circuits may be static or dynamic. Outputs of static logic circuits are logical functions of the inputs. In contrast, a control signal, such as a clock signal, may control outputs of dynamic logic circuits so that the outputs are not necessarily functions of the inputs.
The logic circuits may include combinations of, for example, complementary metal oxide semiconductor (CMOS) circuits. CMOS circuits may include n- and p-channel transistors (referred to as n- and p-type transistors) that include source, drain, and gate terminals, also referred to as first, second, and control terminals, respectively. Other types of transistors may also be used.
The n- and p-type transistors may act as switches that are either open or closed. Sources and drains of n- and p-type transistors communicate when the devices are closed and do not communicate when the devices are open. An n-type transistor is open when the gate is at a logical 0, and closed when the gate is at a logical 1. A p-type transistor is closed when the gate is at a logical 0, and open when the gate is at a logical 1. A logical 1 may be represented by a supply voltage potential Vdd, and a logical 0 may be represented by a reference voltage potential Vss, such as ground.
Referring now to FIGS. 2A and 2B, an exemplary clock gater 24 is illustrated. The clock gater 24 may include an OR gate 50 that receives an enable signal and/or a test enable signal. The enable signal (E) may enable/disable a clock signal (CLK) to a circuit that is not under test, and the test enable signal (TE) may enable/disable a clock signal to a circuit under test. A latch 52 of the clock gater 24 may buffer the clock signal based on outputs of the OR gate 50. For example, if either the enable or test enable signals provide a logical 1 to the OR gate 50, the latch 52 buffers the clock signal in a feedback circuit 53, otherwise, the latch 52 passes the clock signal.
A NAND gate 54 may output an inverted clock signal based on the clock signal and outputs of the latch 52. An inverter 56 may provide the output clock signal (QCK) by inverting NAND gate outputs. The output clock signal is distributed to a clock-gated circuit. The output clock signal is therefore delayed by at least four logic stages (OR gate 50, latch 52, NAND gate 54, and inverter 56).
In FIG. 2B, the OR gate 50 may include n- and p-type transistors 60, 62, 64, 66 and inverter 68 that collectively provide a logical 1 when either the enable or test enable signals are high. The latch 52 includes n- and p-type transistors 70-81 of a feedback circuit 53 that selectively provide the clock signal output based on the enable signal. The NAND gate 54 includes n- and p-type transistors 90-93 that provide an output based on the buffered clock signal from the latch 52 and the current clock signal. The inverter 56 may include n- and p-type transistors 96-97 to invert NAND gate signals.
The latch output and clock signal that are supplied to the respective inputs of the NAND gate 54 may be in a race condition in which the clock signal waits until the latch output arrives. If the latch output arrives later than the clock signal, then the output clock signal will be driven by the enable signal and not by the clock signal, which can result in a clock skew problem. To allow enough time to provide the latch output before the clock signal, the setup time of the enable signal with respect to the clock signal may be increased. In other words, the clock signal and/or the latch output are effectively delayed through the addition of setup operations in the latch 52 and/or OR gate 50 so that both are received in the NAND gate 54 simultaneously.